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[default is %s]
%s
specify variant of 960 architecture
-b add code to collect statistics about branches taken
-link-relax preserve individual alignment directives so linker
can do relaxing (b.out format only)
-no-relax don't alter compare-and-branch instructions for
long displacements
specify variant of SPARC architecture
-bump warn when assembler switches architectures
-sparc ignored
--enforce-aligned-data force .long, etc., to be aligned correctly
-relax relax jumps and branches (default)
-no-relax avoid changing any jumps and branches
%s
input file : %s
options passed :
output file : %s
target : %s
time stamp : %s
D30V options:
-O Make adjacent short instructions parallel if possible.
-n Warn about all NOPs inserted by the assembler.
-N Warn about NOPs inserted after word multiplies.
-c Warn about symbols whoes names match register names.
-C Opposite of -C. -c is the default.
TIC4X options:
-mcpu=CPU -mCPU select architecture variant. CPU can be:
30 - TMS320C30
31 - TMS320C31, TMS320LC31
32 - TMS320C32
33 - TMS320VC33
40 - TMS320C40
44 - TMS320C44
-mrev=REV set cpu hardware revision (integer numbers).
Combinations of -mcpu and -mrev will enable/disable
the appropriate options (-midle2, -mlowpower and
-menhanced) according to the selected type
-mbig select big memory model
-msmall select small memory model (default)
-mregparm select register parameters (default)
-mmemparm select memory parameters
-midle2 enable IDLE2 support
-mlowpower enable LOPOWER and MAXSPEED support
-menhanced enable enhanced opcode support
constraint violations
for constraint violations
instructions might violate contraints
might violate contraints
EXTENSION is combination of:
Registers will not need any prefix.
Registers will require a `$'-prefix.
emulate output (default %s)
Record the cpu type
-EB assemble code for a big-endian cpu
-EL assemble code for a little-endian cpu
-FIXDD assemble code for fix data dependency
-G gpnum assemble code for setting gpsize and default is 8 byte
-KPIC assemble code for PIC
-NWARN assemble code for no warning message for fix data dependency
-O0 assembler will not perform any optimizations
-SCORE3 assemble code for target is SCORE3
-SCORE5 assemble code for target is SCORE5
-SCORE5U assemble code for target is SCORE5U
-SCORE7 assemble code for target is SCORE7, this is default setting
-USE_R1 assemble code for no warning message when using temp register r1
-V Sunplus release version
-V print assembler version number
-Qy, -Qn ignored
-march=score3 assemble code for target is SCORE3
-march=score7 assemble code for target is SCORE7, this is default setting
S390 options:
-mregnames Allow symbolic names for registers
-mwarn-areg-zero Warn about zero base/index registers
-mno-regnames Do not allow symbolic names for registers
-m31 Set file format to 31 bit format
-m64 Set file format to 64 bit format
ops were: --32/--64/--x32 generate 32bit/64bit/x32 code
--MD FILE write dependency information in FILE (default none)
--alternate initially turn on alternate macro syntax
--compress-debug-sections
compress DWARF debug sections using zlib
--debug-prefix-map OLD=NEW
map OLD to NEW in debug information
--defsym SYM=VAL define symbol SYM to given value
--disp-size-default-22 branch displacement with unknown size is 22 bits (default)
--disp-size-default-32 branch displacement with unknown size is 32 bits
--divide do not treat `/' as a comment character
--divide ignored
--execstack require executable stack for this object
--fatal-warnings treat warnings as errors
--fix-v4bx Allow BX in ARMv4 code
--gdwarf-2 generate DWARF2 debugging information
--gstabs generate STABS debugging information
--gstabs+ generate STABS debug info with GNU extensions
--hash-size= set the hash table size close to
--help show this message and exit
--itbl INSTTBL extend instruction set to include instructions
matching the specifications defined in file INSTTBL
--listing-cont-lines set the maximum number of continuation lines used
for the output data column of the listing
--listing-lhs-width set the width in words of the output data column of
the listing
--listing-lhs-width2 set the width in words of the continuation lines
of the output data column; ignored if smaller than
the width of the first line
--listing-rhs-width set the max width in characters of the lines from
the source file
--m32bit-doubles [default]
--m64bit-doubles
--march= Generate code for . Valid choices for
are v0_v10, v10, v32 and common_v10_v32.
--mbig-endian-data
--mint-register=
--mlittle-endian-data [default]
--mpid
--mrelax
--msmall-data-limit
--muse-conventional-section-names
--muse-renesas-section-names [default]
--no-underscore User symbols do not have any prefix.
--nocompress-debug-sections
don't compress DWARF debug sections
--noexecstack don't require executable stack for this object
--pic Enable generation of position-independent code.
--reduce-memory-overheads
prefer smaller memory use at the cost of longer
assembly times
--size-check=[error|warning]
ELF .size directive check (default --size-check=error)
--statistics print various measured statistics from execution
--strip-local-absolute strip local absolute symbols
--target-help show target specific options
--traditional-format Use same format as native assembler when possible
--underscore User symbols are normally prepended with underscore.
--version print assembler version number and exit
--warn don't suppress warnings
-D produce assembler debugging messages
-EB assemble code for a big-endian cpu
-EB,-big produce big endian code and data
-EL generate code for little endian mode (default)
-EB generate code for big endian mode
-mwarn-expand warn if pseudo operations are expanded
-mxp enable i860XP support (disabled by default)
-mintel-syntax enable Intel syntax (default to AT&T/SVR4)
-EL assemble code for a little-endian cpu
-EL,-little produce little endian code and data
-I DIR add DIR to search list for .include directives
-Ip synonym for -ignore-parallel-conflicts
-J don't warn about signed overflow
-K warn when differences altered for long displacements
-KPIC generate PIC
-L,--keep-locals keep local symbols (e.g. starting with `L')
-M,--mri assemble in MRI compatibility mode
-N Warn when branches are expanded to jumps.
-O try to optimize code. Implies -parallel
-Q ignored
-Q ignored
-V print assembler version number
-Q ignored
-V print assembler version number
--32/--64 generate 32bit/64bit code
-Q ignored
-V print assembler version number
-k ignored
-R fold data section into text section
-V print assembler version number
-Qy, -Qn ignored
-W --no-warn suppress warnings
-Wnp synonym for -no-warn-explicit-parallel-conflicts
-Wnuh synonym for -no-warn-unmatched-high
-Wp synonym for -warn-explicit-parallel-conflicts
-Wuh synonym for -warn-unmatched-high
-X ignored
-Z generate object file even after errors
-c print a warning if a comment is found
-f skip whitespace and comment preprocessing
-fixed-special-register-names
Allow only the original special register names.
-g --gen-debug generate debugging information
-globalize-symbols Make all symbols global.
-gnu-syntax Turn off mmixal syntax compatibility.
-h, -H Don't execute, print this help text. Deprecated.
-ignore-parallel-conflicts do not check parallel instructions
-linker-allocated-gregs If there's no suitable GREG definition for the operands of an instruction, let the linker resolve.
-m32r disable support for the m32rx instruction set
-m32r2 support the extended m32r2 instruction set
-m32rx support the extended m32rx instruction set
-mQ - enable relaxation at assembly time. DANGEROUS!
-mP - enable polymorph instructions
-mall-opcodes accept all AVR opcodes, even if not supported by MCU
-mno-skip-bug disable warnings for skipping two-word instructions
(default for avr4, avr5)
-mno-wrap reject rjmp/rcall instructions with 8K wrap-around
(default for avr3, avr5)
-march=ARCH enable instructions from architecture ARCH
-march=CPU[,+EXTENSION...]
generate code for CPU and EXTENSION, CPU is one of:
-march=ms1-16-002 allow ms1-16-002 instructions (default)
-march=ms1-16-003 allow ms1-16-003 instructions
-march=ms1-64-001 allow ms1-64-001 instructions
-march=ms2 allow ms2 instructions
-mavxscalar=[128|256] encode scalar AVX instructions with specific vector
length
-mbig-endian generate big-endian code
-mcpu= specify the name of the target CPU
-mdsbt code uses DSBT addressing
-mextension enable extension opcode support
-mfdpic assemble for the FDPIC ABI
-mindex-reg support pseudo index registers
-mip2022 restrict to IP2022 insns
-mip2022ext permit extended IP2022 insn
-mlittle-endian generate little-endian code
-mmnemonic=[att|intel] use AT&T/Intel mnemonic
-mnaked-reg don't require `%%' prefix for registers
-mno-bcond17 disable b disp17 instruction
-mno-dsbt code does not use DSBT addressing
-mno-fdpic/-mnopic disable -mfdpic
-mno-pic code addressing is position-dependent
-mno-stld23 disable st/ld offset23 instruction
-mold-gcc support old (<= 2.8.1) versions of gcc
-mpic code addressing is position-independent
-mpid=far code uses position-independent data addressing,
GOT accesses use far DP addressing
-mpid=near code uses position-independent data addressing,
GOT accesses use near DP addressing
-mpid=no code uses position-dependent data addressing
-mrelax Enable relaxation
-msse-check=[none|error|warning]
check SSE instructions
-msse2avx encode SSE instructions with VEX prefix
-msyntax=[att|intel] use AT&T/Intel syntax
-mtune=CPU optimize for CPU, CPU is one of:
-mv850 The code is targeted at the v850
-mv850e The code is targeted at the v850e
-mv850e1 The code is targeted at the v850e1
-mv850e2 The code is targeted at the v850e2
-mv850e2v3 The code is targeted at the v850e2v3
-mwarn-signed-overflow Warn if signed immediate values overflow
-mwarn-unsigned-overflow Warn if unsigned immediate values overflow
-n Do not optimize code alignment
-q quieten some warnings
-nIp synonym for -no-ignore-parallel-conflicts
-no-bitinst disallow the M32R2's extended bit-field instructions
-no-expand Do not expand GETA, branches, PUSHJ or JUMP
into multiple instructions.
-no-ignore-parallel-conflicts check parallel instructions for
-no-merge-gregs Do not merge GREG definitions with nearby values.
-no-parallel disable -parallel
-no-predefined-syms Do not provide mmixal built-in constants.
Implies -fixed-special-register-names.
-no-warn-explicit-parallel-conflicts do not warn when parallel
-no-warn-unmatched-high do not warn about missing low relocs
-nocpp ignored
-nosched disable scheduling restrictions
-o OBJFILE name the object-file output OBJFILE (default a.out)
-parallel try to combine instructions in parallel
-relax Create linker relaxable code.
-s ignored
-w ignored
-warn-explicit-parallel-conflicts warn when parallel instructions
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc
-x Do not warn when an operand to GETA, a branch,
PUSHJ or JUMP is not known to be within range.
The linker will catch any errors. Implies
-linker-allocated-gregs. -xauto automagically remove dependency violations (default)
-xnone turn off dependency violation checking
-xdebug debug dependency violation checker
-xdebugn debug dependency violation checker but turn off
dependency violation checking
-xdebugx debug dependency violation checker and turn on
dependency violation checking
@FILE read options from FILE
%s; (Requires %s; requested architecture is %s.) *input_line_pointer == '%c' 0x%02x
ARM-specific assembler options:
Blackfin specific assembler options:
FR30 specific command line options:
GNU assembler version %s (%s)
using BFD version %s. Insn slot not set in unwind record. M32C specific command line options:
M32R specific command line options:
MMIX-specific command line options:
RX specific command line options:
Score-specific assembler options:
V850 options:
XC16X specific command line options:
XSTORMY16 specific command line options:
Z8K options:
-z8001 generate segmented code
-z8002 generate unsegmented code
-linkrelax create linker relaxable code
branch relocation truncate (0x%x) [-2^9 ~ 2^9] branch relocation truncate (0x%x) [-2^19 ~ 2^19] branch relocation truncate (0x%x) [-2^9 ~ 2^9] !%s does not use a sequence number !samegp reloc against symbol without .prologue: %s "%d" (instance number %d of a %s label) ".else" without matching ".if" ".elseif" after ".else" ".elseif" without matching ".if" ".endif" without ".if" ".option" directive conflicts with initial definition ".option" directive must appear before any instructions ".option" directive overrides command-line (default) value # Example of `%s' instructions
.sect .text
_start:
# bars register # conflicts length #4 not valid on H8/300. # # # $DPR_BYTE not supported in this context $DPR_GOT not supported in this context $DPR_HWORD not supported in this context $DPR_WORD not supported in this context $DSBT_INDEX must be used with __c6xabi_DSBT_BASE $DSBT_INDEX not supported in this context $GOT not supported in this context $PCR_OFFSET not supported in this context $dbg and $depc are disabled when DEBUG is off $hi and $lo are disabled when MUL and DIV are off $mb0, $me0, $mb1, and $me1 are disabled when COP is off % operator needs absolute expression %d error%s, %d warning%s, generating bad object file %d error%s, %d warning%s, no object file generated %d warnings, treating warnings as errors %s %s (%08lx %08lx) after %s (%08lx %08lx) %s -- `%s' %s -- statement `%s' ignored %s ISA does not support DSP ASE %s ISA does not support DSP R2 ASE %s ISA does not support MCU ASE %s ISA does not support MT ASE %s ISA does not support SmartMIPS %s ISA does not support SmartMIPS ASE %s NOP inserted %s `%s' already has an alias `%s' %s argument must be a string %s for `%s' %s instruction, operand %d doesn't match %s isa does not support 64-bit floating point registers %s isa does not support 64-bit registers %s may not occupy the delay slot of another branch insn. %s must have a constant value %s out of domain (%d is not a multiple of %d) %s out of range (%d is not between %d and %d) %s out of range (0x%s is not between 0x%s and 0x%s) %s register same as write-back base %s relocations do not fit in %d bytes %s relocations do not fit in %d bytes
%s shortened to %s %s symbol recursion stopped at second appearance of '%s' %s unsupported %s without %s %s: data size %ld
%s: global symbols not supported in common sections %s: no such section %s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? %s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? %s: total time in assembly: %ld.%06ld
%s: unexpected function type: %d %s: unrecognized processor name %s: would close weakref loop: %s %s:%u: bad return from bfd_install_relocation: %x %u-byte relocation cannot be applied to %u-byte field '%.*s' instruction not at start of execute packet '%.*s' instruction not in a software pipelined loop '%.*s' instruction not supported on this architecture '%.*s' instruction not supported on this functional unit '%.*s' instruction not supported on this functional unit for this architecture '%s' is not repeatable. Resulting behavior is undefined. '%s' is only available in DD2.0 or higher. '%s' may not be bundled with other instructions. '%s': only the NOP instruction can be issued in parallel on the m32r ')' required ',' expected 'APSR', 'CPSR' or 'SPSR' expected 'ASR' required 'LSL' or 'ASR' required 'LSL' required 'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher. 'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher. '[' expected '[' expected after PLD mnemonic '[' expected after PLI mnemonic ']' expected 'd.%s' must be 8-byte aligned 'entry_num' must be absolute number in [0,31] '||' after predicate '||' not followed by instruction '||^' without previous SPMASK '}' expected at end of 'option' field (PC)+ unpredictable (plt) is only valid on branch targets (unknown reason) * -%s conflicts with the other architecture options, which imply -%s -(PC) unpredictable -- unterminated string --abi=[32|64] set size of expanded SHmedia operands and object
file type
--shcompact-const-crange emit code-range descriptors for constants in
SHcompact code sections
--no-mix disallow SHmedia code in the same section as
constants and SHcompact code
--no-expand do not expand MOVI, PT, PTA or PTB instructions
--expand-pt32 with -abi=64, expand PT, PTA and PTB instructions
to 32 bits only
--absolute-literals option not supported in this Xtensa configuration --density option is ignored --fdpic generate an FDPIC object file
--generics is deprecated; use --transform instead --gstabs is not supported for ia64 --hash-size needs a numeric argument --isa=[shmedia set as the default instruction set for SH64
| SHmedia
| shcompact
| SHcompact]
--no-density option is ignored --no-generics is deprecated; use --no-transform instead --no-relax is deprecated; use --no-transform instead --no-underscore is invalid with a.out format --nops needs a numeric argument --pic is invalid for this object format --relax is deprecated; use --transform instead -32 create 32 bit object file
-64 create 64 bit object file
-32 create o32 ABI object file (default)
-n32 create n32 ABI object file
-64 create 64 ABI object file
-64 is supported for ELF format only -EL generate code for a little endian machine
-EB generate code for a big endian machine
--little-endian-data generate code for a machine having big endian
instructions and little endian data.
-G may not be used in position-independent code -G may not be used with SVR4 PIC code -G n Put data <= n bytes in the small data area
-G not supported in this configuration. -KPIC generate PIC
-V print assembler version number
-undeclared-regs ignore application global register usage without
appropriate .register directive (default)
-no-undeclared-regs force error on application global register usage
without appropriate .register directive
-q ignored
-Qy, -Qn ignored
-s ignored
-KPIC, -call_shared generate SVR4 position independent code
-call_nonpic generate non-PIC code that can operate with DSOs
-mvxworks-pic generate VxWorks position independent code
-non_shared do not generate code that can operate with DSOs
-xgot assume a 32 bit GOT
-mpdr, -mno-pdr enable/disable creation of .pdr sections
-mshared, -mno-shared disable/enable .cpload optimization for
position dependent (non shared) code
-mabi=ABI create ABI conformant object file for:
-R option not supported on this target. -TSO use Total Store Ordering
-PSO use Partial Store Ordering
-RMO use Relaxed Memory Ordering
-call_nonpic is supported only for ELF format -call_shared is supported only for ELF format -expand-pt32 invalid together with -no-expand -expand-pt32 only valid with -abi=64 -k generate PIC
-l use 1 word for refs to undefined symbols [default 2]
-pic, -k generate position independent code
-S turn jbsr into jsr
--pcrel never turn PC-relative branches into absolute jumps
--register-prefix-optional
recognize register names without prefix character
--bitwise-or do not treat `|' as a comment character
--base-size-default-16 base reg without size is 16 bits
--base-size-default-32 base reg without size is 32 bits (default)
--disp-size-default-16 displacement with unknown size is 16 bits
--disp-size-default-32 displacement with unknown size is 32 bits (default)
-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.
-no-mCPU don't generate code specific to CPU.
For -mCPU and -no-mCPU, CPU must be one of:
-mPIC Mark generated file as using large position independent code
-m[no-]%-16s enable/disable%s architecture extension
-mabi is supported for ELF format only -maltivec generate code for AltiVec
-mvsx generate code for Vector-Scalar (VSX) instructions
-me300 generate code for PowerPC e300 family
-me500, -me500x2 generate code for Motorola e500 core complex
-me500mc, generate code for Freescale e500mc core complex
-me500mc64, generate code for Freescale e500mc64 core complex
-mspe generate code for Motorola SPE instructions
-mtitan generate code for AppliedMicro Titan core complex
-mregnames Allow symbolic names for registers
-mno-regnames Do not allow symbolic names for registers
-march=%s is not compatible with the selected ABI -march= set architecture
-mcpu= set cpu [default %s]
-mcpu= Specify the CPU version
-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}
-mdouble Mark generated file as using double precision FP insns
-mdsp generate DSP instructions
-mno-dsp do not generate DSP instructions
-mdspr2 generate DSP R2 instructions
-mno-dspr2 do not generate DSP R2 instructions
-mdword Mark generated file as using a 8-byte stack alignment
-me Redirect errors to a file
-merrors-to-file
-mfar-mode | -mf Use extended addressing
-mfdpic Assemble for the FDPIC ABI
-mfix-loongson2f-jump work around Loongson2F JUMP instructions
-mfix-loongson2f-nop work around Loongson2F NOP errata
-mfix-vr4120 work around certain VR4120 errata
-mfix-vr4130 work around VR4130 mflo/mfhi errata
-mfix-24k insert a nop after ERET and DERET instructions
-mfix-cn63xxp1 work around CN63XXP1 PREF errata
-mgp32 use 32-bit GPRs, regardless of the chosen ISA
-mfp32 use 32-bit FPRs, regardless of the chosen ISA
-msym32 assume all symbols have 32-bit values
-O0 remove unneeded NOPs, do not swap branches
-O remove unneeded NOPs and swap branches
--trap, --no-break trap exception on div by 0 and mult overflow
--break, --no-trap break exception on div by 0 and mult overflow
-mfp32 used with -mdmx -mfp32 used with -mips3d -mfp32 used with a 64-bit ABI -mfp64 used with a 32-bit ABI -mfp64 used with a 32-bit fpu -mfpr-32 Mark generated file as only using 32 FPRs
-mfpr-64 Mark generated file as using all 64 FPRs
-mgp32 used with a 64-bit ABI -mgp64 used with a 32-bit ABI -mgp64 used with a 32-bit processor -mgpr-32 Mark generated file as only using 32 GPRs
-mgpr-64 Mark generated file as using all 64 GPRs
-mhard-float allow floating-point instructions
-msoft-float do not allow floating-point instructions
-msingle-float only allow 32-bit floating-point operations
-mdouble-float allow 32-bit and 64-bit floating-point operations
--[no-]construct-floats [dis]allow floating point values to be constructed
-mips1 generate MIPS ISA I instructions
-mips2 generate MIPS ISA II instructions
-mips3 generate MIPS ISA III instructions
-mips4 generate MIPS ISA IV instructions
-mips5 generate MIPS ISA V instructions
-mips32 generate MIPS32 ISA instructions
-mips32r2 generate MIPS32 release 2 ISA instructions
-mips64 generate MIPS64 ISA instructions
-mips64r2 generate MIPS64 release 2 ISA instructions
-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:
-mips16 generate mips16 instructions
-no-mips16 do not generate mips16 instructions
-mips16 cannot be used with -micromips -mlibrary-pic Mark generated file as using position indepedent code for libraries
-mmcu generate MCU instructions
-mno-mcu do not generate MCU instructions
-mmedia Mark generated file as using media insns
-mmicromips generate microMIPS instructions
-mno-micromips do not generate microMIPS instructions
-mmicromips cannot be used with -mips16 -mmt generate MT instructions
-mno-mt do not generate MT instructions
-mmuladd Mark generated file as using multiply add/subtract insns
-mno-dword Mark generated file as using a 4-byte stack alignment
-mno-pack Do not allow instructions to be packed
-mnopic Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic
-mpack Allow instructions to be packed
-mpic Mark generated file as using small position independent code
-mppc64, -m620 generate code for PowerPC 620/625/630
-mppc64bridge generate code for PowerPC 64, including bridge insns
-mbooke generate code for 32-bit PowerPC BookE
-ma2 generate code for A2 architecture
-mpower4, -mpwr4 generate code for Power4 architecture
-mpower5, -mpwr5, -mpwr5x
generate code for Power5 architecture
-mpower6, -mpwr6 generate code for Power6 architecture
-mpower7, -mpwr7 generate code for Power7 architecture
-mcell generate code for Cell Broadband Engine architecture
-mcom generate code Power/PowerPC common instructions
-many generate code for any architecture (PWR/PWRX/PPC)
-mrelocatable support for GCC's -mrelocatble option
-mrelocatable-lib support for GCC's -mrelocatble-lib option
-memb set PPC_EMB bit in ELF flags
-mlittle, -mlittle-endian, -le
generate code for a little endian machine
-mbig, -mbig-endian, -be
generate code for a big endian machine
-msolaris generate code for Solaris
-mno-solaris do not generate code for Solaris
-K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags
-V print assembler version number
-Qy, -Qn ignored
-msmartmips generate smartmips instructions
-mno-smartmips do not generate smartmips instructions
-msoft-float Mark generated file as using software FP
-mtomcat-debug Debug tomcat workarounds
-mtomcat-stats Print out stats for tomcat workarounds
-n32 is supported for ELF format only -no-expand only valid with SHcompact or SHmedia -no-mix is invalid without specifying SHcompact or SHmedia -non_shared is supported only for ELF format -nops=count when aligning, more than COUNT nops uses a branch
-shcompact-const-crange is invalid without SHcompact .%s outside of %s ... .COMMon length (%d.) < 0! Ignored. .COMMon length (%ld.) <0! Ignored. .COMMon length (%lu) out of range ignored .EQU must use a label .EXIT must appear within a procedure .REG expression must be a register .REG must use a label .SCOMMon length (%ld.) <0! Ignored. .abort detected. Abandoning ship. .arch requires a matching --march=... option .begin [no-]density is ignored .begin directive with no matching .end directive .begin directive without a preceding .ent directive .begin directive without a preceding .file directive .begin literal is deprecated; use .literal instead .begin/.bend in different segments .bend directive names unknown symbol .bend directive without a preceding .ent directive .bend directive without a preceding .file directive .bss size %d < 0! .bss size %ld < 0! .bss size argument missing
.callinfo is not within a procedure definition .cfi_endproc without corresponding .cfi_startproc .cfi_lsda requires encoding and symbol arguments .cfi_personality requires encoding and symbol arguments .compiler directive missing language and version .compiler directive missing version .cpload not in noreorder section .def pseudo-op used inside of .def/.endef: ignored. .def pseudo-op used inside of .def/.endef; ignored .dim pseudo-op used outside of .def/.endef: ignored. .dim pseudo-op used outside of .def/.endef; ignored .ef with no preceding .function .end [no-]density is ignored .end directive has no name .end directive missing or unknown symbol .end directive names different symbol than .ent .end directive names unknown symbol .end directive without a preceding .ent directive .end directive without a preceding .ent directive. .end directive without a preceding .file directive .end directive without matching .ent .end not in text section .end symbol does not match .ent symbol. .end%c encountered without preceding %s .end%s without preceding .%s .endef pseudo-op used before .def; ignored .endef pseudo-op used outside of .def/.endef: ignored. .endfunc missing for previous .func .endfunc missing for previous .proc .ent directive has no name .ent directive has no symbol .ent directive without matching .end .ent or .aent not in text section. .err encountered .error directive invoked in source file .es without preceding .bs .fail %ld encountered .field count '%d' out of range (1 <= X <= 32) .fill size clamped to %d .fmask outside of .ent .fnend directive without .fnstart .frame outside of .ent .handler directive has no name .ifeqs syntax error .incbin count zero, ignoring `%s' .inst.n operand too big. Use .inst.w instead .largecomm supported only in 64bit mode, producing .comm .linkonce is not supported for this object file format .literal not allowed inside .begin literal region .literal_position inside literal directive; ignoring .ln pseudo-op inside .def/.endef: ignored. .loc before .file .loc outside of .text .loc pseudo-op inside .def/.endef: ignored. .longcall pseudo-op seen when not relaxing .longjump pseudo-op seen when not relaxing .ltorg in section %s paired to .using in section %s .ltorg without prior .using in section %s .machine stack overflow .machine stack underflow .mask outside of .ent .mask/.fmask outside of .ent .name directive has no symbol .name directive not in link (.link) section .option pic%d not supported .pdesc directive has no entry symbol .pdesc directive not in link (.link) section .pdesc doesn't match with last .ent .pdesc has a bad entry symbol .popsection without corresponding .pushsection; ignored .previous without corresponding .section; ignored .profiler pseudo requires at least two operands. .prologue directive without a preceding .ent directive .prologue within prologue .ref outside .csect .sblock may be used for initialized sections only .scl pseudo-op used outside of .def/.endef ignored. .scl pseudo-op used outside of .def/.endef; ignored .sect: subsection name ignored .set pop with no .set push .set syntax invalid
.size expression for %s does not evaluate to a constant .size pseudo-op used outside of .def/.endef ignored. .size pseudo-op used outside of .def/.endef; ignored .space or .fill with negative value, ignored .space repeat count is negative, ignored .space repeat count is zero, ignored .space specifies non-absolute value .space/.bes repeat count is negative, ignored .space/.bes repeat count is zero, ignored .stab%c is not supported .stab%c: description field '%x' too big, try a different debug format .stab%c: ignoring non-zero other field .stab%c: missing comma .stabx of storage class stsym must be within .bs/.es .syntax %s requires command-line option `--no-underscore' .syntax %s requires command-line option `--underscore' .tag pseudo-op used outside of .def/.endef ignored. .tag pseudo-op used outside of .def/.endef; ignored .tag requires a structure tag .tag target '%s' undefined .tc not in .toc section .tc with no label .type pseudo-op used outside of .def/.endef ignored. .type pseudo-op used outside of .def/.endef; ignored .unwind_save does not support this kind of register .usect: non-zero alignment flag ignored .usepv directive has no name .usepv directive has no type .uses does not refer to a local symbol in the same section .uses pseudo-op seen when not relaxing .uses target does not refer to a local symbol in the same section .using: base address expression illegal or too complex .val expression is too complex .val pseudo-op used outside of .def/.endef ignored. .val pseudo-op used outside of .def/.endef; ignored .var may only be used within a macro definition .vframepsp is meaningless, assuming .vframesp was meant .vliw unavailable when VLIW is disabled. .warning directive invoked in source file .word %s-%s+%s didn't fit .word case-table handling failed: table too large 0x%lx out range of signed 32bit displacement 0x%lx: "%s" type = %ld, class = %d, segment = %d
16-bit jump out of range 3-bit immediate out of range 32-bit conditional branch generated 32bit mode not supported on `%s'. 32bit x86_64 is only supported for ELF 48-bit microMIPS instructions are not supported 5-bit field must be absolute 5-bit immediate too large 6-bit displacement out of range 6-bit immediate out of range 62-bit relocation not yet implemented 64bit mode not supported on `%s'. 68040 and 68851 specified; mmu instructions may assemble incorrectly 8 byte instruction in delay slot 8 byte jump instruction with delay slot 8-bit displacement out of range 8-bit immediate out of range : PC-relative operand can't be a constant : TLS operand can't be a constant : There are only 32 f registers; [0-31] : There are only 32 single precision f registers; [0-31] : There are only 64 f registers; [0-63] : asr number must be between 0 and 31 : asr number must be between 16 and 31 : expecting %asrN : invalid ASI expression : invalid ASI name : invalid ASI number : invalid cpreg name : invalid membar mask expression : invalid membar mask name : invalid membar mask number : invalid prefetch function expression : invalid prefetch function name : invalid prefetch function number : invalid siam mode expression : invalid siam mode number : rd on write only ancillary state register : unrecognizable hyperprivileged register : unrecognizable privileged register : unrecognizable v9a ancillary state register : unrecognizable v9a or v9b ancillary state register :b not permitted; defaulting to :w :lower16: not allowed this instruction :upper16: not allowed instruction :upper16: not allowed this instruction assemble for floating point ABI assemble for architecture assemble for CPU assemble for FPU architecture ,X