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orc_program_set_line orc_program_set_2d orc_program_set_constant_n orc_program_set_n_multiple orc_program_set_n_minimum orc_program_set_n_maximum orc_program_set_constant_m orc_program_set_backup_function orc_program_set_backup_name orc_program_get_name orc_program_set_type_name orc_program_set_var_alignment orc_program_set_sampling_type orc_program_find_var_by_name orc_program_get_asm_code orc_program_get_error orc_program_set_error orc_program_add_temporary orc_program_dup_temporary orc_program_add_source_full orc_program_add_source orc_program_add_destination_full orc_program_add_destination orc_program_add_constant orc_program_add_constant_float orc_program_add_constant_int64 orc_program_add_constant_double orc_program_add_constant_str __ctype_b_loc orc_program_add_parameter orc_program_add_parameter_float orc_program_add_parameter_double orc_program_add_parameter_int64 orc_program_add_accumulator orc_program_get_max_array_size orc_program_get_max_accumulator_size orc_get_data_cache_sizes orc_get_cpu_family_model_stepping orc_get_cpu_name orc_program_take_code orc_target_c_get_typedefs orc_x86_get_regname_sse orc_program_new orc_program_new_dss orc_program_new_ds orc_program_new_ass orc_program_new_as orc_program_new_from_static_bytecode orc_program_free orc_program_reset orc_program_append_ds orc_program_append orc_program_append_2 orc_program_append_str orc_program_append_str_2 orc_program_append_ds_str orc_program_append_dds_str orc_rule_register orc_x86_emit_mov_memoffset_sse orc_sse_restore_mxcsr orc_x86_emit_mov_memindex_sse orc_x86_emit_mov_sse_memoffset orc_sse_set_mxcsr orc_x86_get_regname orc_x86_get_regnum orc_x86_get_regname_8 orc_x86_get_regname_16 orc_x86_get_regname_64 orc_x86_get_regname_ptr orc_x86_get_regname_size orc_x86_emit_modrm_memoffset_old orc_x86_emit_modrm_memoffset orc_x86_emit_modrm_memindex orc_x86_emit_modrm_memindex2 orc_x86_emit_modrm_reg orc_x86_emit_rex orc_x86_assemble_copy_check orc_x86_get_output_insn orc_x86_emit_cpuinsn_size orc_x86_emit_push orc_x86_emit_pop orc_x86_emit_cpuinsn_imm orc_x86_emit_cpuinsn_load_memoffset orc_x86_emit_cpuinsn_store_memoffset orc_x86_emit_cpuinsn_load_memindex orc_x86_emit_add_reg_reg_shift orc_x86_emit_cpuinsn_imm_reg orc_x86_emit_cmp_imm_reg orc_x86_emit_cpuinsn_imm_memoffset orc_x86_emit_cmp_imm_memoffset orc_x86_emit_dec_memoffset orc_x86_emit_cpuinsn_reg_memoffset_s orc_x86_emit_cpuinsn_reg_memoffset orc_x86_emit_cpuinsn_reg_memoffset_8 orc_x86_emit_cpuinsn_memoffset_reg orc_x86_emit_add_imm_reg orc_x86_emit_cpuinsn_branch orc_x86_emit_cpuinsn_align orc_x86_emit_cpuinsn_label orc_x86_emit_cpuinsn_none orc_x86_emit_rep_movs orc_x86_emit_epilogue orc_x86_emit_cpuinsn_memoffset orc_x86_get_regname_mmx orc_x86_emit_mov_memoffset_reg orc_x86_emit_mov_reg_memoffset orc_x86_do_fixups orc_x86_calculate_offsets orc_x86_emit_mov_memoffset_mmx orc_x86_emit_mov_memindex_mmx orc_x86_emit_mov_mmx_memoffset orc_sse_load_constant orc_x86_emit_prologue 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orc_mips_emit_sh orc_mips_emit_sb orc_mips_emit_lw orc_mips_emit_lwr orc_mips_emit_lwl orc_mips_emit_lh orc_mips_emit_lb orc_mips_emit_lbu orc_mips_emit_jr orc_mips_emit_addiu orc_mips_emit_addi orc_mips_emit_add orc_mips_emit_move orc_mips_emit_addu orc_mips_emit_addu_qb orc_mips_emit_addu_ph orc_mips_emit_addq_s_ph orc_mips_emit_adduh_r_qb orc_mips_emit_ori orc_mips_emit_or orc_mips_emit_and orc_mips_emit_lui orc_mips_emit_sub orc_mips_emit_subu_qb orc_mips_emit_subq_s_ph orc_mips_emit_subq_ph orc_mips_emit_subu_ph orc_mips_emit_srl orc_mips_emit_sll orc_mips_emit_sra orc_mips_emit_shll_ph orc_mips_emit_shra_ph orc_mips_emit_shrl_ph orc_mips_emit_andi orc_mips_emit_prepend orc_mips_emit_append orc_mips_emit_mul orc_mips_emit_mul_ph orc_mips_emit_mtlo orc_mips_emit_extr_s_h orc_mips_emit_slt orc_mips_emit_movn orc_mips_emit_repl_ph orc_mips_emit_replv_qb orc_mips_emit_replv_ph orc_mips_emit_preceu_ph_qbr orc_mips_emit_precr_qb_ph orc_mips_emit_precrq_qb_ph orc_mips_emit_cmp_lt_ph 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0.4.31 vector # %d: %s
assertion failed: value >= 0 ../orc/orcbytecode.c assertion failed: 0 emulating ../orc/orcexecutor.c dest vartype tmp %d opcode %s %p %p %p src ptr %p stride %d m_index %d m %d var %d: %d %d %d ../orc/orccompiler.c at insn %d %s XDG_RUNTIME_DIR HOME TMPDIR /tmp ../orc/orccodemem.c sys ORC_DEBUG orc-0.4.31 debug init ../orc/orcdebug.c ORC_CODE emulate debug randomize loadb loadw loadl loadq loadoffb loadoffw loadoffl loadupdb loadupib loadpb loadpw loadpl loadpq ldresnearl ldreslinl storeb storew storel storeq addb addssb addusb andb andnb cmpeqb subb subssb subusb xorb addw addssw addusw andw andnw cmpeqw mullw mulhsw mulhuw subw subssw subusw xorw addl andl andnl cmpeql cmpgtsl subl xorl andq andnq xorq select0ql select1ql select0lw select1lw select0wb select1wb mergebw mergewl mergelq copyb copyw copyl copyq shlw shruw shrsw shll shrul shrsl shlq shruq shrsq convsbw convubw convssswb convsuswb convuuswb convwb convswl convuwl convssslw convql convslq convulq mulsbw mulubw mulswl muluwl accw accl accsadubl maxsl minsl maxul minul convlw signw absb absw absl swapw swapl swapwl swapq swaplq splitql splitlw splitwb avgsl avgul shlb shrsb shrub mulll mullb mulhsb mulhub addssl subssl addusl subusl convhwb convhlw splatw3q splatbw splatbl div255w divluw convsuslw mulslq cmpeqq cmpgtsq mululq addq subq addf subf mulf divf minf maxf sqrtf cmpeqf cmpltf cmplef convfl convlf addd subd muld divd mind maxd sqrtd cmpeqd cmpltd cmpled convdl convld convfd convdf mulhsl mulhul signb signl variables instructions %d: %s %d %d %d %d %s.dup%d bad vartype allocating code memory compiling for target "%s" finished compiling (success) finished compiling (fail) few many .function .backup .init .flags mult min max .source align .dest .accumulator .temp .param .longparam .const .floatparam .doubleparam _%d.%s NONE ERROR WARNING INFO LOG mips neon altivec sse mmx error: duplicate variable name: %s
error: destination "%s" written multiple times
error: source "%s" read multiple times
error: variable "%s" used before being written
register overflow for %s register no code generation rule for %s attempt to run program that failed to compile Unaligned array for src%d, program %s Unaligned array for dest%d, program %s no temporary register available failed to create write/exec map Failed to create write and exec mmap regions. This is probably because SELinux execmem check is enabled (good) and $TMPDIR and $HOME are mounted noexec (bad). initializing compiler for program "%s" program %s failed to compile, reason: %s %d: %s size %d type %d alloc %d size mismatch, opcode %s dest[%d] is %d should be %d size mismatch, opcode %s src[%d] is %d should be %d opcode %s requires const or param source using uninitialized temp var at line %d using src var as dest at line %d using const var as dest at line %d using param var as dest at line %d accumulating opcode to non-accumulator dest at line %d non-accumulating opcode to accumulator dest at line %d Compilation disabled, using backup Compilation disabled, using emulation no code generation rule for %s on target %s program %s failed to compile, reason %d error: line %d: .backup without function name
error: line %d: .init without function name
error: line %d: .n mult requires multiple value
error: line %d: .n min requires multiple value
error: line %d: .n max requires multiple value
error: line %d: unknown .n token '%s'
error: line %d: .source align requires alignment value
error: line %d: unknown .dest token '%s'
error: line %d: unknown .source token '%s'
error: line %d: unknown directive: %s
error: line %d: too %s arguments for %s (expected %d)
error: line %d: unknown opcode: %s
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orc_memset *
orc_memcpy * orc_executor_emulate orc_compiler_get_constant_reg orc_compiler_get_temp_reg orc_compiler_check_sizes get_load_opcode_for_size get_loadp_opcode_for_size get_store_opcode_for_size orc_compiler_rewrite_vars orc_program_compile_full orc_code_region_allocate_codemem_anon_map orc_code_region_allocate_codemem orc_code_region_get_free_chunk bytecode_append_int orc_bytecode_from_program _orc_debug_init
/* begin Orc C target preamble */
#define ORC_CLAMP(x,a,b) ((x)<(a) ? (a) : ((x)>(b) ? (b) : (x)))
#define ORC_ABS(a) ((a)<0 ? -(a) : (a))
#define ORC_MIN(a,b) ((a)<(b) ? (a) : (b))
#define ORC_MAX(a,b) ((a)>(b) ? (a) : (b))
#define ORC_SB_MAX 127
#define ORC_SB_MIN (-1-ORC_SB_MAX)
#define ORC_UB_MAX (orc_uint8) 255
#define ORC_UB_MIN 0
#define ORC_SW_MAX 32767
#define ORC_SW_MIN (-1-ORC_SW_MAX)
#define ORC_UW_MAX (orc_uint16)65535
#define ORC_UW_MIN 0
#define ORC_SL_MAX 2147483647
#define ORC_SL_MIN (-1-ORC_SL_MAX)
#define ORC_UL_MAX 4294967295U
#define ORC_UL_MIN 0
#define ORC_CLAMP_SB(x) ORC_CLAMP(x,ORC_SB_MIN,ORC_SB_MAX)
#define ORC_CLAMP_UB(x) ORC_CLAMP(x,ORC_UB_MIN,ORC_UB_MAX)
#define ORC_CLAMP_SW(x) ORC_CLAMP(x,ORC_SW_MIN,ORC_SW_MAX)
#define ORC_CLAMP_UW(x) ORC_CLAMP(x,ORC_UW_MIN,ORC_UW_MAX)
#define ORC_CLAMP_SL(x) ORC_CLAMP(x,ORC_SL_MIN,ORC_SL_MAX)
#define ORC_CLAMP_UL(x) ORC_CLAMP(x,ORC_UL_MIN,ORC_UL_MAX)
#define ORC_SWAP_W(x) ((((x)&0xffU)<<8) | (((x)&0xff00U)>>8))
#define ORC_SWAP_L(x) ((((x)&0xffU)<<24) | (((x)&0xff00U)<<8) | (((x)&0xff0000U)>>8) | (((x)&0xff000000U)>>24))
#define ORC_SWAP_Q(x) ((((x)&ORC_UINT64_C(0xff))<<56) | (((x)&ORC_UINT64_C(0xff00))<<40) | (((x)&ORC_UINT64_C(0xff0000))<<24) | (((x)&ORC_UINT64_C(0xff000000))<<8) | (((x)&ORC_UINT64_C(0xff00000000))>>8) | (((x)&ORC_UINT64_C(0xff0000000000))>>24) | (((x)&ORC_UINT64_C(0xff000000000000))>>40) | (((x)&ORC_UINT64_C(0xff00000000000000))>>56))
#define ORC_PTR_OFFSET(ptr,offset) ((void *)(((unsigned char *)(ptr)) + (offset)))
#define ORC_DENORMAL(x) ((x) & ((((x)&0x7f800000) == 0) ? 0xff800000 : 0xffffffff))
#define ORC_ISNAN(x) ((((x)&0x7f800000) == 0x7f800000) && (((x)&0x007fffff) != 0))
#define ORC_DENORMAL_DOUBLE(x) ((x) & ((((x)&ORC_UINT64_C(0x7ff0000000000000)) == 0) ? ORC_UINT64_C(0xfff0000000000000) : ORC_UINT64_C(0xffffffffffffffff)))
#define ORC_ISNAN_DOUBLE(x) ((((x)&ORC_UINT64_C(0x7ff0000000000000)) == ORC_UINT64_C(0x7ff0000000000000)) && (((x)&ORC_UINT64_C(0x000fffffffffffff)) != 0))
#ifndef ORC_RESTRICT
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
#define ORC_RESTRICT restrict
#elif defined(__GNUC__) && __GNUC__ >= 4
#define ORC_RESTRICT __restrict__
#else
#define ORC_RESTRICT
#endif
#endif
/* end Orc C target preamble */
too many temporary variables allocated too many source variables allocated too many destination variables allocated too many parameter variables allocated too many accumulator variables allocated #ifndef _ORC_INTEGER_TYPEDEFS_
#define _ORC_INTEGER_TYPEDEFS_
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
#include
typedef int8_t orc_int8;
typedef int16_t orc_int16;
typedef int32_t orc_int32;
typedef int64_t orc_int64;
typedef uint8_t orc_uint8;
typedef uint16_t orc_uint16;
typedef uint32_t orc_uint32;
typedef uint64_t orc_uint64;
#define ORC_UINT64_C(x) UINT64_C(x)
#elif defined(_MSC_VER)
typedef signed __int8 orc_int8;
typedef signed __int16 orc_int16;
typedef signed __int32 orc_int32;
typedef signed __int64 orc_int64;
typedef unsigned __int8 orc_uint8;
typedef unsigned __int16 orc_uint16;
typedef unsigned __int32 orc_uint32;
typedef unsigned __int64 orc_uint64;
#define ORC_UINT64_C(x) (x##Ui64)
#define inline __inline
#else
#include
typedef signed char orc_int8;
typedef short orc_int16;
typedef int orc_int32;
typedef unsigned char orc_uint8;
typedef unsigned short orc_uint16;
typedef unsigned int orc_uint32;
#if INT_MAX == LONG_MAX
typedef long long orc_int64;
typedef unsigned long long orc_uint64;
#define ORC_UINT64_C(x) (x##ULL)
#else
typedef long orc_int64;
typedef unsigned long orc_uint64;
#define ORC_UINT64_C(x) (x##UL)
#endif
#endif
typedef union { orc_int16 i; orc_int8 x2[2]; } orc_union16;
typedef union { orc_int32 i; float f; orc_int16 x2[2]; orc_int8 x4[4]; } orc_union32;
typedef union { orc_int64 i; double f; orc_int32 x2[2]; float x2f[2]; orc_int16 x4[4]; } orc_union64;
#endif
#ifndef ORC_RESTRICT
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
#define ORC_RESTRICT restrict
#elif defined(__GNUC__) && __GNUC__ >= 4
#define ORC_RESTRICT __restrict__
#else
#define ORC_RESTRICT
#endif
#endif
#ifndef ORC_INTERNAL
#if defined(__SUNPRO_C) && (__SUNPRO_C >= 0x590)
#define ORC_INTERNAL __attribute__((visibility("hidden")))
#elif defined(__SUNPRO_C) && (__SUNPRO_C >= 0x550)
#define ORC_INTERNAL __hidden
#elif defined (__GNUC__)
#define ORC_INTERNAL __attribute__((visibility("hidden")))
#else
#define ORC_INTERNAL
#endif
#endif
((orc_union64 *)(ex->src_ptrs[%d]))->i ((orc_union32 *)(ex->params+%d))->i int m = ex->params[ORC_VAR_A1];
#if defined(__APPLE__) && __GNUC__ == 4 && __GNUC_MINOR__ == 2 && defined (__i386__)
const %s * ORC_RESTRICT ptr%d;
ptr%d = ORC_PTR_OFFSET(%s, %s * j);
%*s for (i = 0; i < n; i++) {
((orc_union32 *)ex->dest_ptrs[%d])->i = (%s + ((orc_union32 *)ex->dest_ptrs[%d])->i) & 0xffff;
ex->accumulators[%d] = (%s & 0xffff);
((orc_union32 *)ex->dest_ptrs[%d])->i += (orc_uint%d)%s;
%s = ORC_CLAMP_SB(%s + %s);
%s = ORC_CLAMP_UB((orc_uint8)%s + (orc_uint8)%s);
%s = ((orc_uint8)%s + (orc_uint8)%s + 1)>>1;
%s = ORC_MAX((orc_uint8)%s, (orc_uint8)%s);
%s = ORC_MIN((orc_uint8)%s, (orc_uint8)%s);
%s = ((orc_uint32)(orc_uint8)%s * (orc_uint32)(orc_uint8)%s) >> 8;
%s = ((orc_uint8)%s) << %s;
%s = ((orc_uint8)%s) >> %s;
%s = ORC_CLAMP_SB(%s - %s);
%s = ORC_CLAMP_UB((orc_uint8)%s - (orc_uint8)%s);
%s = ORC_CLAMP_SW(%s + %s);
%s = ORC_CLAMP_UW((orc_uint16)%s + (orc_uint16)%s);
%s = ((orc_uint16)%s + (orc_uint16)%s + 1)>>1;
%s = ORC_MAX((orc_uint16)%s, (orc_uint16)%s);
%s = ORC_MIN((orc_uint16)%s, (orc_uint16)%s);
%s = ((orc_uint32)((orc_uint16)%s) * (orc_uint32)((orc_uint16)%s)) >> 16;
%s = ((orc_uint16)%s) << %s;
%s = ((orc_uint16)%s) >> %s;
%s = ORC_CLAMP_SW(%s - %s);
%s = ORC_CLAMP_UW((orc_uint16)%s - (orc_uint16)%s);
%s = ((orc_uint32)%s) + ((orc_uint32)%s);
%s = ORC_CLAMP_SL((orc_int64)%s + (orc_int64)%s);
%s = ORC_CLAMP_UL((orc_int64)(orc_uint32)%s + (orc_int64)(orc_uint32)%s);
%s = ((orc_int64)%s + (orc_int64)%s + 1)>>1;
%s = ((orc_uint64)(orc_uint32)%s + (orc_uint64)(orc_uint32)%s + 1)>>1;
%s = ORC_MAX((orc_uint32)%s, (orc_uint32)%s);
%s = ORC_MIN((orc_uint32)%s, (orc_uint32)%s);
%s = (((orc_uint32)%s) * ((orc_uint32)%s)) & 0xffffffff;
%s = ((orc_int64)%s * (orc_int64)%s) >> 32;
%s = ((orc_uint64)(orc_uint32)%s * (orc_uint64)(orc_uint32)%s) >> 32;
%s = ((orc_uint32)%s) << %s;
%s = ((orc_uint32)%s) >> %s;
%s = ((orc_uint32)%s) - ((orc_uint32)%s);
%s = ORC_CLAMP_SL((orc_int64)%s - (orc_int64)%s);
%s = ORC_CLAMP_UL((orc_int64)(orc_uint32)%s - (orc_int64)(orc_uint32)%s);
%s = (%s == %s) ? (~0) : 0;
%s = (%s > %s) ? (~0) : 0;
%s = ((orc_uint64)%s) + ((orc_uint64)%s);
%s = ((orc_uint64)%s) - ((orc_uint64)%s);
%s = ((orc_uint64)%s) << %s;
%s = ((orc_uint64)%s) >> %s;
%s = ((orc_uint16)%s)>>8;
%s = ORC_MIN((orc_uint16)%s,ORC_SB_MAX);
%s = ORC_MIN((orc_uint16)%s,ORC_UB_MAX);
%s = ((orc_uint32)%s)>>16;
%s = ORC_CLAMP((orc_uint32)%s,0,ORC_SW_MAX);
%s = ORC_CLAMP_UW((orc_uint32)%s);
%s = ORC_CLAMP_SL((orc_uint64)%s);
%s = ORC_CLAMP_UL((orc_uint64)%s);
%s = ((orc_uint16)((orc_uint8)%s)) * ((orc_uint16)((orc_uint8)%s));
%s = ((orc_uint32)((orc_uint16)%s)) * ((orc_uint32)((orc_uint16)%s));
%s = ((orc_int64)%s) * ((orc_int64)%s);
%s = ((orc_uint64)((orc_uint32)%s)) * ((orc_uint64)((orc_uint32)%s));
_src1.i = ORC_DENORMAL(%s);
_src2.i = ORC_DENORMAL(%s);
%s = ORC_DENORMAL(_dest1.i);
%s = (%s == %s) ? (~0) : 0;
%s = (%s < %s) ? (~0) : 0;
%s = (%s <= %s) ? (~0) : 0;
_src1.i = ORC_DENORMAL_DOUBLE(%s);
_src2.i = ORC_DENORMAL_DOUBLE(%s);
%s = ORC_DENORMAL_DOUBLE(_dest1.i);
%s = (%s == %s) ? ORC_UINT64_C(~0) : 0;
%s = (%s < %s) ? ORC_UINT64_C(~0) : 0;
%s = (%s <= %s) ? ORC_UINT64_C(~0) : 0;
%s = ((orc_union64 *)(ex->src_ptrs[%d]))->i;
%s = (ex->params[%d] & 0xffffffff) | ((orc_uint64)(ex->params[%d + (ORC_VAR_T1 - ORC_VAR_P1)]) << 32);
%s = 0x%08x; /* %d or %gf */
%s = ORC_UINT64_C(0x%08x%08x); /* %gf */
var%d = ptr%d[offset + i];
var%d = ptr%d[offset + i + %s];
var%d = ptr%d[(offset + i)>>1];
var%d = ((offset + i)&1) ? ((orc_uint8)ptr%d[(offset + i)>>1] + (orc_uint8)ptr%d[((offset + i)>>1)+1] + 1)>>1 : ptr%d[(offset + i)>>1];
var%d = (i&1) ? ((orc_uint8)ptr%d[i>>1] + (orc_uint8)ptr%d[(i>>1)+1] + 1)>>1 : ptr%d[i>>1];
var%d = ptr%d[(%s + (offset + i)*%s)>>16];
var%d = ptr%d[(%s + i*%s)>>16];
int tmp = %s + (offset + i) * %s;
var%d = ((orc_uint8)ptr%d[tmp>>16] * (256-((tmp>>8)&0xff)) + (orc_uint8)ptr%d[(tmp>>16)+1] * ((tmp>>8)&0xff))>>8;
orc_union32 a = ptr%d[tmp>>16];
orc_union32 b = ptr%d[(tmp>>16)+1];
var%d.x4[%d] = ((orc_uint8)a.x4[%d] * (256-((tmp>>8)&0xff)) + (orc_uint8)b.x4[%d] * ((tmp>>8)&0xff))>>8;
ptr%d[offset + i] = var%d;
%s = %s + ORC_ABS((orc_int32)(orc_uint8)%s - (orc_int32)(orc_uint8)%s);
%s = ((%s&0xff) << 8) | (%s&0xff);
%s = ((((orc_uint32)%s)&0xff) << 24) | ((((orc_uint32)%s)&0xff)<<16) | ((((orc_uint32)%s)&0xff) << 8) | (((orc_uint32)%s)&0xff);
%s = ((((orc_uint64)%s)>>48) << 48) | ((((orc_uint64)%s)>>48)<<32) | ((((orc_uint64)%s)>>48) << 16) | ((((orc_uint64)%s)>>48));
%s = ((orc_uint16)(((orc_uint16)(%s+128)) + (((orc_uint16)(%s+128))>>8)))>>8;
%s = ((%s&0xff) == 0) ? 255 : ORC_CLAMP_UB(((orc_uint16)%s)/((orc_uint16)%s&0xff));
%s = ORC_DENORMAL(_dest.i);
if (tmp == 0x80000000 && !(%s&0x80000000)) tmp = 0x7fffffff;
if (tmp == 0x80000000 && !(%s & ORC_UINT64_C(0x8000000000000000))) tmp = 0x7fffffff;
_src1.i = ORC_DENORMAL(%s);
_src2.i = ORC_DENORMAL(%s);
if (ORC_ISNAN(_src1.i)) %s = _src1.i;
else if (ORC_ISNAN(_src2.i)) %s = _src2.i;
else %s = (_src1.f < _src2.f) ? _src1.i : _src2.i;
else %s = (_src1.f > _src2.f) ? _src1.i : _src2.i;
_src1.i = ORC_DENORMAL_DOUBLE(%s);
_src2.i = ORC_DENORMAL_DOUBLE(%s);
if (ORC_ISNAN_DOUBLE(_src1.i)) %s = _src1.i;
else if (ORC_ISNAN_DOUBLE(_src2.i)) %s = _src2.i;
%s = ((%s&0x0000ffffU) << 16) | ((%s&0xffff0000U) >> 16);
%s = ((%s&ORC_UINT64_C(0x00000000ffffffff)) << 32) | ((%s & ORC_UINT64_C(0xffffffff00000000)) >> 32);
code generation rule for %s only works with constant offset unimplemented corner case in %s too many constants allocated ERROR_MMX direct UNALLOCATED func_%p d1 ex->params[%d] ../orc/orcprogram-c.c var%d.x2[%d] var%d.x4[%d] var%d.i var%d var%d.x2f[%d] var%d.x4f[%d] var%d.f unknown opcode: %s ../orc/orcprogram.c unknown opcode: %s at line %d orc_int8 orc_union16 orc_union32 orc_union64 void
%s (OrcExecutor *ex)
%*s int i;
int j;
int n = ex->n;
int n = %d;
int m = %d;
volatile %s var%d;
#else
%s var%d;
#endif
%s * ORC_RESTRICT ptr%d;
%s var%d = { 0 };
%s var%d = 0;
for (j = 0; j < m; j++) {
ptr%d = (%s *)%s;
%*s /* %d: %s */
No rule for: %s on target %s %*s %*s }
*%s = (%s & 0xffff);
*%s = %s;
ex->accumulators[%d] = %s;
%s = ORC_ABS(%s);
%s = %s;
%s = (%s * %s) & 0xff;
%s = (%s * %s) >> 8;
%s = ORC_CLAMP(%s,-1,1);
%s = %s + %s;
%s = (%s + %s + 1)>>1;
%s = (%s * %s) & 0xffff;
%s = (%s * %s) >> 16;
%s = %s - %s;
%s = ORC_MAX(%s, %s);
%s = ORC_MIN(%s, %s);
%s = %s & %s;
%s = (~%s) & %s;
%s = %s | %s;
%s = %s ^ %s;
%s = %s >> %s;
%s = (orc_uint8)%s;
%s = ORC_CLAMP_SB(%s);
%s = ORC_CLAMP_UB(%s);
%s = (orc_uint16)%s;
%s = ORC_CLAMP_SW(%s);
%s = ORC_CLAMP_UW(%s);
%s = (orc_uint32)%s;
%s = ORC_CLAMP_SL(%s);
%s = ORC_CLAMP_UL(%s);
%s = %s * %s;
%s = ORC_SWAP_W(%s);
%s = ORC_SWAP_L(%s);
%s = ORC_SWAP_Q(%s);
{
orc_union32 _src1;
orc_union32 _src2;
orc_union32 _dest1;
_src2.f _src1.f _dest1.f = %s + %s;
}
_dest1.f = %s - %s;
_dest1.f = %s * %s;
_dest1.f = %s / %s;
_dest1.f = sqrt(%s);
orc_union64 _src1;
orc_union64 _src2;
orc_union64 _dest1;
%s = ex->params[%d];
expected param or constant var%d = ptr%d[i];
var%d = ptr%d[i + %s];
var%d = ptr%d[i>>1];
int tmp = %s + i * %s;
ptr%d[i] = var%d;
orc_union64 _src;
_src.i = %s;
%s = _src.x2[1];
%s = _src.x2[0];
orc_union32 _src;
orc_union16 _src;
%s = _src1.f;
orc_union32 _dest;
_dest.f = _src1.f;
int tmp;
tmp = (int)%s;
%s = tmp;
tmp = %s;
orc_union64 _dest;
_dest.x2[0] = %s;
_dest.x2[1] = %s;
%s = _dest.i;
orc_union16 _dest;
failed to find opcode "%s" ../orc/orcrule.c convusswb convusslw convuuslw convsssql convsusql convussql convuusql ldresnearb ldreslinb bad size ../orc/orcsse.c ../orc/orcrules-sse.c bad load size %d xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11 xmm12 xmm13 xmm14 xmm15 d2 d3 d4 c1 c2 c3 c4 c5 c6 c7 c8 p1 p2 p3 p4 p5 p6 p7 p8 t10 t11 t12 t13 t14 t15 iPhihhj(xT4PP@PPPPPPPPPPPPPPPPPPPPPPPPPp,,,,,,,,,,,,\xH4 4
4 4 4 4 4 4 4 4 4 4 t
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
sse_rule_loadpX orc_x86_emit_mov_sse_memoffset orc_x86_emit_mov_memindex_sse orc_x86_emit_mov_memoffset_sse orc_rule_register c_rule_loadpX c_get_name_float c_get_name_int orc_compiler_c_assemble orc_program_append_dds_str orc_program_append_ds_str orc_program_append_str_2 orc_program_append_str orc_program_append_2 orc_program_append orc_program_append_ds short jump too long %d got tmp %d unhandled max var size %d ../orc/orcprogram-sse.c ../orc/orcx86insn.c ../orc/orcmmx.c # loading constant %d 0x%08x
.global %s
.p2align 4
.p2align %d
$%d, %%%s, %d(%%%s), %d(%%%s,%%%s,%d), %%%s %d(%%%s) %d%c %s %s%s%s
bad size %d # LOOP SHIFT %d
../orc/orcrules-mmx.c rax rcx rdx rbx rsp rbp rsi rdi r8 r9 r10 r11 r12 r13 r14 r15 al ch dh bh eax ecx edx ebx esp ebp esi edi r8d r9d r10d r11d r12d r13d r14d r15d frame_pointer short_jumps 64bit code generation rule for %s only works with constant or parameter shifts code generation rule for %s only works with constant shifts could not find alignment variable unimplemented: stride on pointer stored in memory assertion failed: opcode->code != 0 %d: relaxing at %d,%04x diff %d %d: unrelaxing at %d,%04x diff %d # loading constant %08x %08x %08x %08x
register operand on memory instruction ІІІІ @0`Ї||<<<|8 pmaxud ?8 pcmpgtq 78 addps X subps \ mulps Y divps ^ sqrtps Q addpd f X subpd f \ mulpd f Y divpd f ^ sqrtpd f Q cmpeqps cmpeqpd f cmpltps cmpltpd f cmpleps cmplepd f cvttps2dq [ cvttpd2dq f cvtdq2ps [ cvtdq2pd cvtps2pd Z cvtpd2ps f Z minps ] minpd f ] maxps _ maxpd f _ psraw q psrlw q psllw q psrad r psrld r pslld r psrlq s psllq s psrldq s pslldq s pshufd f p pshuflw p pshufhw p palignr f : pinsrw movd n movq ~ movdqa f o movdqu o movhps pextrw : movd ~ movq f movdqa f movdqu movntdq f ldmxcsr
stmxcsr
add add add
add or or or
or adc adc adc
adc sbb sbb sbb
sbb and and and
# and ! sub sub sub
+ sub ) xor xor xor
3 xor 1 cmp cmp cmp
; cmp 9 jo p jno q jc r jnc s jz t jnz u jbe v ja w js x jns y jp z jnp { jl | jge } jle ~ jg jmp ret retq emms w rdtsc 1 nop rep movsb rep movsw f rep movsl push P pop X movzx
movw
f movl
mov
mov movb movw f movl mov test
testl leal
leaq
imul
imull incl decl sar sar and % pshufw p movq o movq endbr32 endbr64 orc_x86_insn_output_asm orc_x86_calculate_offsets orc_x86_insn_output_immediate orc_x86_insn_output_modrm orc_x86_insn_output_opcode f output_opcode get_shift orc_compiler_sse_init sse_rule_splitwb vaddubm vaddsbs vaddubs vand vavgsb vavgub vcmpequb vcmpgtsb vmaxsb vmaxub vminsb vminub vor vsububm vsubsbs vsububs vxor vadduhm vaddshs vadduhs vavgsh vavguh vcmpequh vcmpgtsh vmaxsh vmaxuh vminsh vminuh vsubuhm vsubshs vsubuhs vadduwm vaddsws vadduws vavgsw vavguw vcmpequw vcmpgtsw vmaxsw vmaxuw vminsw vminuw vsubuwm vsubsws vsubuws vaddfp vsubfp vmaxfp vminfp vcmpeqfp xxland xxsel xvcpsgnsp vcmpequd xvcpsgndp xvadddp xvsubdp xvmuldp xvdivdp xvcmpeqdp ../orc/orcprogram-mmx.c lvewx %s, 0, %s
vperm vspltb %s, %s, %i
vsplth %s, %s, %i
vspltw %s, %s, %i
vspltisb %s, %d
vspltish %s, %d
vspltisw %s, %d
lvebx %s, 0, %s
lvehx %s, 0, %s
lvx %s, 0, %s
../orc/orcrules-altivec.c Rule only works with consts lvebx %s, %s, %s
lvehx %s, %s, %s
lvewx %s, %s, %s
lvx %s, %s, %s
stvebx %s, 0, %s
stvehx %s, 0, %s
stvewx %s, 0, %s
stvewx %s, %s, %s
stvx %s, 0, %s
bad store size %d vslb vsrab vsrb vslh vsrah vsrh vslw vsraw vsrw r0 r1 r2 r3 r4 r5 r6 r7 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 mmxext 3dnow 3dnowext H H p H H H H H H H H H H $L" ,# l! l!x&&x'x&(x&x&x&(x&x&x&x&x&x&x&* powerpc_rule_storeX powerpc_rule_loadoffX powerpc_rule_loadX get_shift orc_compiler_mmx_init vcmpgtfp vcmpgefp %s %s, %s, %s
vaddudm vsubudm vcmpgtsd vandc vpkshss vpkswss vpkshus vpkswus vpkuhus vpkuwus vpkuhum vpkuwum vmulesb vmulosb vmrghh vmrglh vmuleub vmuloub vmulesh vmulosh vmrghw vmrglw vmuleuh vmulouh vmulesw vmulosw vmuleuw vmulouw vmrghb vmrglb vsum4ubs vcfsx %s %s, %s, %d
.quad .%s,.TOC.@tocbase,0
.%s:
stdu %s, %d(%s)
stwu %s, %d(%s)
li %s, %d
addi %s, %s, %d
%s %s, %s, %s, %s
vmladduhm %s %s, %s
vupkhsb vupklsb vupkhsh vupklsh ld %s, %d(%s)
lwz %s, %d(%s)
lvsl %s, %s, %s
lvsr %s, %s, %s
ERROR
too many fixups ../orc/orcpowerpc.c addi %s, %s, %df - %s
vmaddfp xvdivsp vctsxs vspltish %s, 8
xvsqrtsp xvsqrtdp xvcmpgtdp xvcmpgedp xvcvsxddp xvcvdpsp vsro vspltisb %s, -1
xvmindp xvmaxdp xvcvdpsxws xvcvspdp ble- %d%c
bdnz+ %d%c
cmplwi %s, %d
blt %d%c
andi. bgt %d%c
srawi%s %s, %s, %d
mtctr %s
slw %s, %s, %s
blr
# load constants
# load invariants
stw %s, %d(%s)
# load inner constants
addic. %s, %s, %d
add %s, %s, %s
std %s, %d(%s)
b %d%c
lvsr %s, 0, %s
lvsl %s, 0, %s
mtvscr %s %s
.long 0x00000000
.long 0x%08x
../orc/orcprogram-neon.c unhandled max array size %d vbic vadd.i8 shift too large ../orc/orcrules-neon.c vqadd.s8 vqadd.u8 vrhadd.s8 vrhadd.u8 vceq.i8 vcgt.s8 vorr vmax.s8 vmax.u8 vmin.s8 vmin.u8 vmul.i8 vsub.i8 vqsub.s8 vqsub.u8 veor vadd.i16 vqadd.s16 vqadd.u16 vrhadd.s16 vrhadd.u16 vceq.i16 vcgt.s16 vmax.s16 vmax.u16 vmin.s16 vmin.u16 vmul.i16 vsub.i16 vqsub.s16 vqsub.u16 vadd.i32 vqadd.s32 vqadd.u32 vrhadd.s32 vrhadd.u32 vceq.i32 vcgt.s32 vmax.s32 vmax.u32 vmin.s32 vmin.u32 vmul.i32 vsub.i32 vqsub.s32 vqsub.u32 vabs.s8 vabs.s16 vabs.s32 vmov.i8 %s, #%d
vmov.i16 %s, #0x%04x
vorr.i16 %s, #0x%04x
vmov.i32 %s, #0x%08x
vorr.i32 %s, #0x%08x
pld%s [%s, #%d]
vst1.64 %s, [%s]%s
bad aligned store size %d vst1.8 { %s, %s }, [%s]%s
vst1.8 %s, [%s]%s
vst1.%d %s[0], [%s]%s
vpaddl.u16 %s, %s
vpaddl.u32 %s, %s
vst1.16 %s[%d], [%s]
vpadd.u32 %s, %s, %s
vst1.32 %s[%d], [%s]
pop %s
vmsr fpscr, %s
vmrs %s, fpscr
push %s
loadX used with non src/dest unimplemented vld1.64 %s, [%s]%s
bad aligned load size %d vld1.8 { %s, %s }, [%s]%s
vld1.8 %s, [%s]%s
bad unaligned load size %d vld1.%d %s[0], [%s]%s
vld1.8 {%s[],%s[]}, [%s]
shift negative %s %s, %s, #%d
vneg.s8 vld1.16 {%s[],%s[]}, [%s]
vld1.32 {%s[],%s[]}, [%s]
vld1.32 %s[0], [%s]%s
vld1.32 %s[1], [%s]%s
vshl.u8 vshl.s8 vshl.u16 vshl.s16 vshl.u32 vshl.s32 vshl.i8 vshr.s8 vshr.u8 vshl.i16 vshr.s16 vshr.u16 vshl.i32 vshr.s32 vshr.u32 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 d0 d5 d6 d7 d9 d10 d11 d12 d13 d14 d15 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 vsx v2.07 unhandled max accumulator size %d vst1.64 { %s, %s, %s, %s }, [%s,:256]%s
vst1.64 { %s, %s }, [%s,:128]%s
vst1.8 { %s, %s, %s, %s }, [%s]%s
vld1.64 { %s, %s, %s, %s }, [%s,:256]%s
vld1.64 { %s, %s }, [%s,:128]%s
vld1.8 { %s, %s, %s, %s }, [%s]%s
shift rule only works with constants and params 64-bit constants not implemented unimplemented load of constant %d çwwww orc_neon_rule_xorl orc_neon_rule_subusl orc_neon_rule_subssl orc_neon_rule_subl orc_neon_rule_orl orc_neon_rule_mulll orc_neon_rule_minul orc_neon_rule_minsl orc_neon_rule_maxul orc_neon_rule_maxsl orc_neon_rule_copyl orc_neon_rule_cmpgtsl orc_neon_rule_cmpeql orc_neon_rule_avgul orc_neon_rule_avgsl orc_neon_rule_andl orc_neon_rule_addusl orc_neon_rule_addssl orc_neon_rule_addl orc_neon_rule_absl orc_neon_rule_xorw orc_neon_rule_subusw orc_neon_rule_subssw orc_neon_rule_subw orc_neon_rule_orw orc_neon_rule_mullw orc_neon_rule_minuw orc_neon_rule_minsw orc_neon_rule_maxuw orc_neon_rule_maxsw orc_neon_rule_copyw orc_neon_rule_cmpgtsw orc_neon_rule_cmpeqw orc_neon_rule_avguw orc_neon_rule_avgsw orc_neon_rule_andw orc_neon_rule_addusw orc_neon_rule_addssw orc_neon_rule_addw orc_neon_rule_absw orc_neon_rule_xorb orc_neon_rule_subusb orc_neon_rule_subssb orc_neon_rule_subb orc_neon_rule_orb orc_neon_rule_mullb orc_neon_rule_minub orc_neon_rule_minsb orc_neon_rule_maxub orc_neon_rule_maxsb orc_neon_rule_copyb orc_neon_rule_cmpgtsb orc_neon_rule_cmpeqb orc_neon_rule_avgub orc_neon_rule_avgsb orc_neon_rule_andb orc_neon_rule_addusb orc_neon_rule_addssb orc_neon_rule_addb orc_neon_rule_absb orc_neon_rule_shift neon_rule_storeX neon_rule_loadX orc_neon_emit_loadiq neon_rule_loadpX get_align_var get_shift orc_neon_load_constants_outer neon_add_strides orc_neon_save_accumulators orc_neon_load_constants_inner orc_compiler_neon_init powerpc_add_fixup
/* begin Orc C target preamble */
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef signed short int16_t;
typedef unsigned short uint16_t;
typedef signed int int32_t;
typedef unsigned int uint32_t;
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
#define ORC_RESTRICT restrict
typedef struct _OrcProgram OrcProgram;
typedef struct _OrcExecutor OrcExecutor;
#define ORC_N_VARIABLES 20
#define ORC_N_REGISTERS 20
#define ORC_OPCODE_N_ARGS 4
struct _OrcExecutor {
OrcProgram *program;
int n;
int counter1;
int counter2;
int counter3;
void *arrays[ORC_N_VARIABLES];
int params[ORC_N_VARIABLES];
/* OrcVariable vars[ORC_N_VARIABLES]; */
/* OrcVariable *args[ORC_OPCODE_N_ARGS]; */
};
#define ORC_CLAMP(x,a,b) ((x)<(a) ? (a) : ((x)>(b) ? (b) : (x)))
#define ORC_ABS(a) ((a)<0 ? -(a) : (a))
#define ORC_MIN(a,b) ((a)<(b) ? (a) : (b))
#define ORC_MAX(a,b) ((a)>(b) ? (a) : (b))
#define ORC_SB_MAX 127
#define ORC_SB_MIN (-1-ORC_SB_MAX)
#define ORC_UB_MAX 255
#define ORC_UB_MIN 0
#define ORC_SW_MAX 32767
#define ORC_SW_MIN (-1-ORC_SW_MAX)
#define ORC_UW_MAX 65535
#define ORC_UW_MIN 0
#define ORC_SL_MAX 2147483647
#define ORC_SL_MIN (-1-ORC_SL_MAX)
#define ORC_UL_MAX 4294967295U
#define ORC_UL_MIN 0
#define ORC_CLAMP_SB(x) ORC_CLAMP(x,ORC_SB_MIN,ORC_SB_MAX)
#define ORC_CLAMP_UB(x) ORC_CLAMP(x,ORC_UB_MIN,ORC_UB_MAX)
#define ORC_CLAMP_SW(x) ORC_CLAMP(x,ORC_SW_MIN,ORC_SW_MAX)
#define ORC_CLAMP_UW(x) ORC_CLAMP(x,ORC_UW_MIN,ORC_UW_MAX)
#define ORC_CLAMP_SL(x) ORC_CLAMP(x,ORC_SL_MIN,ORC_SL_MAX)
#define ORC_CLAMP_UL(x) ORC_CLAMP(x,ORC_UL_MIN,ORC_UL_MAX)
#define ORC_SWAP_W(x) ((((x)&0xff)<<8) | (((x)&0xff00)>>8))
#define ORC_SWAP_L(x) ((((x)&0xff)<<24) | (((x)&0xff00)<<8) | (((x)&0xff0000)>>8) | (((x)&0xff000000)>>24))
#define ORC_PTR_OFFSET(ptr,offset) ((void *)(((unsigned char *)(ptr)) + (offset)))
/* end Orc C target preamble */
assertion failed: compiler->n_fixups < ORC_N_FIXUPS assertion failed: label < ORC_N_LABELS unknown data processing type %d const int var%d = 0x80000000;
const unsigned char * restrict ptr%d;
unsigned char * restrict ptr%d;
const int var%d = ex->params[%d];
for (j = 0; j < ex->params[ORC_VAR_A1]; j++) {
ptr%d = ORC_PTR_OFFSET(ex->arrays[%d], ex->params[%d] * j);
ptr%d = ORC_PTR_OFFSET(%s, %s_stride * j);
%*s n1 = ((4 - (int)ptr%d)&0x3) >> %d;
%*s n3 = n & ((1 << %d) - 1);
%*s for (i = 0; i < n1; i++) {
%*s for (i = 0; i < n2; i++) {
%*s for (i = 0; i < n3; i++) {
ex->accumulators[%d] = (var%d & 0xffff);
ex->accumulators[%d] = var%d;
%s = 0x80808080^_saddu4(0x80808080^%s,0x80808080^%s);
%s = 0x7f7f7f7f^_avgu4(0x7f7f7f7f^%s,0x7f7f7f7f^%s);
%s = _cmpgtu4(0x80808080^%s,0x80808080^%s);
%s = 0x80808080^_maxu4(0x80808080^%s,0x80808080^%s);
%s = 0x80808080^_minu4(0x80808080^%s,0x80808080^%s);
%s = 0x80808080^_maxu4(0x7f7f7f7f,_minu4(0x81818181,0x80808080^%s));
%s = 0x80008000^_sadd2(0x80008000^%s,0x80008000^%s);
%s = 0x7fff7fff^_avg2(0x7fff7fff^%s,0x7fff7fff^%s);
%s = _max2(0x80008000^%s,0x80008000^%s);
%s = _min2(0x80008000^%s,0x80008000^%s);
%s = _max2(-1,_min2(1,%s));
%s = 0x80008000^_ssub2(0x80008000^%s,0x80008000^%s);
%s = ORC_CLAMP_UL((int64_t)(uint32_t)%s + (int64_t)(uint32_t)%s);
%s = ((int64_t)%s + (int64_t)%s + 1)>>1;
%s = ((uint64_t)(uint32_t)%s + (uint64_t)(uint32_t)%s + 1)>>1;
%s = ORC_MAX((uint32_t)%s, (uint32_t)%s);
%s = ORC_MIN((uint32_t)%s, (uint32_t)%s);
%s = _loll(_mpy32ll(%s,%s));
%s = _hill(_mpy32ll(%s,%s));
%s = _hill(_mpy32u(%s,%s));
%s = ((uint32_t)%s) >> %s;
%s = ORC_CLAMP((int)%s,-1,1);
%s = ORC_CLAMP_UL((int64_t)(uint32_t)%s - (int64_t)(uint32_t)%s);
%s = (uint8_t)%s * (uint8_t)%s;
%s = (uint16_t)%s * (uint16_t)%s;
%s = 0 /* float disabled %s */;
%s = 0 /* float disabled %s %s */;
%s = _subabs4(0x80808080,0x80808080^%s);
long long x = _mpy2ll(%s,%s);
%s = _pack2(_hill(x),_loll(x));
%s = _packh2(_hill(x),_loll(x));
%s = (%s<<%s) & (~(((1<<%s)-1)<<16 | ((1<<%s)-1)));
%s = _packl4(0,_max2(0xff80ff80,_min2(0x007f007f,%s)));
%s = _packlh2(_swap4(%s),_swap4(%s));
%s = %s + ORC_ABS((int32_t)(uint8_t)%s - (int32_t)(uint8_t)%s);
vzip.8 vzip.16 vtrn.32 vzip.32 vuzp.32 vuzp.16 vuzp.8 vadd.i64 vsub.i64 vmovl.s8 vmovl.u8 vmovl.s16 vmovl.u16 vmovl.s32 vmovl.u32 vmovn.i16 vqmovn.s16 vqmovun.s16 vqmovn.u16 vmovn.i32 vmovn.i64 vqmovn.s32 vqmovun.s32 vqmovn.u32 vqmovn.s64 vqmovun.s64 vqmovn.u64 vmull.s8 vmull.u8 vmull.s16 vmull.u16 vrev16.i8 vrev32.i8 vrev64.i8 vrev32.i16 vrev64.i32 vadd.f32 vsub.f32 vmul.f32 vmax.f32 vmin.f32 vceq.f32 vcvt.s32.f32 vcvt.f32.s32 vadd.f64 vsub.f64 vmul.f64 vdiv.f64 vsqrt.f64 vcvt.f64.f32 vcvt.f32.f64 vrecpe.f32 vrecps.f32 vrsqrte.f32 vrsqrts.f32 ../orc/orcarm.c fixup out of range fixup out of range (%d > 255) const _const (*(%sint8_t *)var%d) _%smem%d%s(var%d) ../orc/orcprogram-c64x-c.c (*(float *)(&var%d)) ((float *)var%d)[i] vshl.i64 %s, %s, #%d
vldr %s, .L%d+%d
vtbl.8 %s, { %s, %s }, %s
vtbl.8 %s, { %s }, %s
bx lr
push { vpush { d%d -d%d}
vpop { pop { .L%d:
nop
b%s .L%d
bad immediate value mov %s, #0x%08x
add %s, %s, #0x%08x
and %s, %s, #%d
cmp %s, %s
asr %s, %s, #%d
lsl %s, %s, #%d
ldr %s, [%s, #%d]
str %s, [%s, #%d]
invalid ARM immediate %08x #0x%08x %s, %s #%d %s, %s %s %s, RRX %s%s%s %s, %s, %s
%s%s%s %s, %s
%s%s %s, %s
, ROR #%d %s%s %s, %s, %s%s
%s%s %s, %s%s
LSL ASR %s%s %s, #%d, %s%s
.word 0x%08x
ldrh %s, [%s, #%d]
%*s ptr%d += %d;
%s ( %s * %s uint%d_t * %s , int %s_stride int %s int n int m const int var%d = %d;
int var%d;
int var%d = 0;
const int var%d = %s;
%*s int n;
%*s int n1, n2, n3;
for (j = 0; j < %d; j++) {
ptr%d = ex->arrays[%d];
ptr%d = (void *)%s;
%*s n = ex->n;
%*s n2 = (n - n1) >> %d;
#pragma MUST_ITERATE(0,%d)
*%s = (var%d & 0xffff);
*%s = var%d;
%s = _add4(%s,%s);
%s = _saddu4(%s,%s);
%s = _avgu4(%s,%s);
%s = _cmpeq4(%s,%s);
%s = _maxu4(%s,%s);
%s = _minu4(%s,%s);
%s = _sub4(%s,%s);
%s = _abs2(%s);
%s = _add2(%s,%s);
%s = _sadd2(%s,%s);
%s = _avg2(%s,%s);
%s = _cmpeq2(%s,%s);
%s = _cmpgt2(%s,%s);
%s = _max2(%s,%s);
%s = _min2(%s,%s);
%s = _shr2(%s,%s);
%s = _shru2(%s,%s);
%s = _sub2(%s,%s);
%s = _ssub2(%s,%s);
%s = _abs(%s);
%s = _sadd(%s,%s);
%s = %s << %s;
%s = _ssub(%s,%s);
%s = _unpklu4(%s);
%s = (int16_t)%s;
%s = (uint16_t)%s;
%s = _packl4(0,%s);
%s = _spacku4(0,%s);
%s = _pack2(0,%s);
%s = _spack2(0,%s);
%s = _pack2(%s, %s);
%s = _packl4(%s, %s);
%s = _packh4(0,%s);
%s = _packh2(0,%s);
%s = _swap4(%s);
vshrn.i16 %s, %s, #%d
vshrn.i32 %s, %s, #%d
vabdl.u8 %s, %s, %s
vpadal.u16 vmull.u32 vshrn.i64 %s, %s, #%d
vmull.s32 vrshrn.u16 %s, %s, #%d
rev rev16 ssat usat ssat16 usat16 pkhbt pkhtb sxtb16 sxtb sxth uxtb16 uxtb uxth sxtab16 sxtab sxtah uxtab16 uxtab uxtah u add16 addsubx subaddx sub16 add8 sub8 add sub adc sbc rsc tst teq cmp cmn mov mvn LSR ip lr pc ne cs cc mi vs vc hi ls gt P??@@`=>QQQQMQ c_get_name_float c_get_name emit_loop get_align_var get_shift orc_compiler_c64x_c_assemble 0 j n P p p p p p p a b c e f g h orc_arm_emit_dp orc_arm_emit_lsl_imm orc_arm_emit_asr_imm orc_arm_emit_add_imm orc_arm_emit_load_imm orc_arm_do_fixups orc_arm_add_fixup orc_arm_emit_label orc_neon_rule_sqrtf orc_neon_rule_divf orc_neon_rule_convfd orc_neon_rule_convdf orc_neon_rule_sqrtd orc_neon_rule_divd orc_neon_rule_muld orc_neon_rule_subd orc_neon_rule_addd orc_neon_rule_convlf orc_neon_rule_convfl orc_neon_rule_cmpeqf orc_neon_rule_minf orc_neon_rule_maxf orc_neon_rule_mulf orc_neon_rule_subf orc_neon_rule_addf orc_neon_rule_select0wb orc_neon_rule_select0lw orc_neon_rule_select0ql orc_neon_rule_swaplq orc_neon_rule_swapwl orc_neon_rule_swapq orc_neon_rule_swapl orc_neon_rule_swapw orc_neon_rule_muluwl orc_neon_rule_mulswl orc_neon_rule_mulubw orc_neon_rule_mulsbw orc_neon_rule_convuusql orc_neon_rule_convsusql orc_neon_rule_convsssql orc_neon_rule_convuuslw orc_neon_rule_convsuslw orc_neon_rule_convssslw orc_neon_rule_convql orc_neon_rule_convlw orc_neon_rule_convuuswb orc_neon_rule_convsuswb orc_neon_rule_convssswb orc_neon_rule_convwb orc_neon_rule_convulq orc_neon_rule_convslq orc_neon_rule_convuwl orc_neon_rule_convswl orc_neon_rule_convubw orc_neon_rule_convsbw orc_neon_rule_xorq orc_neon_rule_subq orc_neon_rule_orq orc_neon_rule_copyq orc_neon_rule_andq orc_neon_rule_addq
/* begin Orc MIPS target preamble */
.abicalls
.set noreorder
/* end Orc MIPS target preamble */
assertion failed: compiler->fixups[i].type == 0 assertion failed: rt == ORC_MIPS_ZERO Could not get optimised instruction order, not emitting loop Don't know how to handle that shift rule only implemented for constants family_id %d model_id %d stepping %d type %d level %d line size %d partitions %d ways %d sets %d L1 D-cache: %d kbytes, %d-way, %d lines/tag, %d line size L1 I-cache: %d kbytes, %d-way, %d lines/tag, %d line size L2 cache: %d kbytes, %d assoc, %d lines/tag, %d line size unhandled vendor %08x %08x %08x t%d ex->dest_ptrs[%d] ex->src_ptrs[%d] ex->arrays[%d] sw %s, %d(%s)
swr %s, %d(%s)
swl %s, %d(%s)
sh %s, %d(%s)
sb %s, %d(%s)
lw %s, %d(%s)
lwr %s, %d(%s)
lwl %s, %d(%s)
lh %s, %d(%s)
lb %s, %d(%s)
lbu %s, %d(%s)
jr %s
addiu %s, %s, %d
addi %s, %s, %d
add %s, %s, %s
addu %s, %s, %s
addu.qb %s, %s, %s
addu.ph %s, %s, %s
addq_s.ph %s, %s, %s
adduh_r.qb %s, %s, %s
ori %s, %s, %d
or %s, %s, %s
and %s, %s, %s
lui %s, %d
sub %s, %s, %s
subu.qb %s, %s, %s
subq_s.ph %s, %s, %s
subq.ph %s, %s, %s
subu.ph %s, %s, %s
srl %s, %s, %d
sll %s, %s, %d
sra %s, %s, %d
shll.ph %s, %s, %d
shra.ph %s, %s, %d
shrl.ph %s, %s, %d
andi %s, %s, %d
prepend %s, %s, %d
append %s, %s, %d
mul %s, %s, %s
mul.ph %s, %s, %s
mtlo %s
extr_s.h %s, $ac%d, %d
slt %s, %s, %s
movn %s, %s, %s
repl.ph %s, %d
replv.qb %s, %s
replv.ph %s, %s
preceu.ph.qbr %s, %s
precr.qb.ph %s, %s, %s
precrq.qb.ph %s, %s, %s
cmp.lt.ph %s, %s
pick.ph %s, %s, %s
packrl.ph %s, %s, %s
wsbh %s, %s
seh %s, %s
pref %d, %d(%s)
vsldoi %s %s, %s, %s, %d
../orc/orcmips.c .L%s%d:
beq bne blez bgtz %s %s, %s, .L%s%d
%s %s, .L%s%d
unknown branch type: 0x%x bltz bgez %s %s, %s, %d
%s %s, %d
unhandled variable size %d ../orc/orcprogram-mips.c loop_shift=%d No rule for %s
.globl %s
not implemented ../orc/orcrules-mips.c insn_shift=%d level %d size %d ../orc/orccpu-x86.c processor string '%s' %s/orcexec.XXXXXX failed to create temp file failed to expand file to size failed to create exec map failed to create write map assertion failed: var < 48 cpuid %d %08x %08x %08x -sse2 -sse3 -ssse3 -sse41 -sse42 -sse4a -sse5 # LOOP shift %d
# %d: %s No rule for: %s
$0 $at $v0 $v1 $a0 $a1 $a2 $a3 $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $t8 $t9 $k0 $k1 $gp $sp $fp $ra c64x-c get_varname_stride orc_code_region_allocate_codemem_dual_map orc_sse_detect_cpuid_amd orc_sse_detect_cpuid_intel orc_x86_detect_cpuid orc_x86_cpuid_handle_family_model_stepping orc_x86_cpuid_get_branding_string
@
@ ` ! " # % ) @ , A B C D E F @ G H 0 I @ J ` K L M N ` ` @ f g @ h x y z { | } handle_cache_descriptor mips_rule_loadp mips_rule_loadupib mips_rule_shruw mips_rule_shrsw mips_rule_shrs mips_rule_store mips_rule_load get_align_var get_shift orc_mips_add_strides orc_mips_emit_loop orc_compiler_orc_mips_init orc_mips_emit_conditional_branch_with_offset orc_mips_add_fixup orc_mips_emit_conditional_branch orc_mips_do_fixups orc_mips_emit_label ;0 1 <1 LT1 h1 |1 1 l1 1 1 ,1 l1 2 2 02 \D2 X2 l2 <2 l2 2 2 2 3 ,3 @3 LT3 h3 |3 3 L3 3 3 3 L3 4 4 04 \D4 X4 l4 ,4 l4 4 4 L4 4 4 5 L 5 45 H5 \5 L p5 5 5 5 <
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